1. Field of the Invention
The invention relates to a flash memory module, a storage apparatus using the flash memory module as a storage medium, and an address translation table verification method for the flash memory module, particularly to those suitable for use in verification of an address translation table used for accessing data stored in a flash memory module.
2. Description of Related Art
Generally, a storage apparatus has a randomly accessible nonvolatile storage medium, such as a magnetic disk or an optical disk.
Meanwhile, collectively erasable nonvolatile semiconductor storage media, such as flash memory, have been being developed with the development of semiconductor techniques. In a flash memory module, a flash memory controller in the module refers to an address translation table to translate a logical page address into a physical page address, and stores data to a flash memory chip. Storage apparatuses that use the flash memory module as a storage medium are considered as more favorable in terms of durability, power-save performance, and access time, etc., than storage apparatuses having a number of small disk drives such as magnetic disks.
A method for preventing inappropriate mapping in an address translation table in a flash memory module exists (see Japanese Patent Laid-Open Publication No. 2003-337757). That conventional technique is designed to prevent inappropriate mapping that may occur when valid logical page address data is garbled into invalid data.
As described above, storage apparatuses using a flash memory module as a storage medium are considered as being able to save more power than those using magnetic disks or similar. However, comparing power consumption values in a currently commercial 2.5 inch hard disk drive and in a 2.5 inch hard disk drive compatible flash memory module in an example, the power consumption value during data writing/reading (R/W) in the flash memory module is 2.9 watt, and that in the hard disk drive is 2.3 watt. The power consumption value in the flash memory module is a little larger than that in the hard disk drive. During idling, the power consumption value in the flash memory module is 2.2 watt, and that in the hard disk drive is 1.2 watt. The power consumption value in the flash memory module is about twice that in the hard disk drive.
A flash memory chip itself consumes a very little power, as the power consumption per chip during idling is on the sub-milliwatt level. Accordingly, a large part of the power consumption in the flash memory module during idling can be considered as being derived from the flash memory controller. Therefore, it is essential to conserve the power consumption in the flash memory controller during idling to take advantage of the low power consumption characteristics of the flash memory chip.
Commonly, a flash memory controller is a CMOS LSI (Complementary Metal Oxide Semiconductor Large Scale Integration). In a CMOS LSI, power consumption can be saved by decreasing power supply voltage or lowering operating frequency. Accordingly, it can be assumed that the power consumption in a flash memory will become lower by decreasing power supply voltage, halting operation, or lowering operating frequency in the flash memory controller.
Meanwhile, an address translation table in a flash memory controller is stored in RAM. For example, SRAM (Static Random Access Memory) is used because high-speed access characteristics are required in RAM. In SRAM, soft errors occur due to radiation in some cases, at a very small rate. If the power consumption in a memory controller is lowered, the possibility that a soft error in data written to an address translation table occurs during low power operation mode increases.
To address the thus caused soft errors, data is guaranteed against soft errors generally by adding error correction information to data stored in an address translation table and verifying the address data and the error correction information added to that address data when reading the data. In other words, accessed data in SRAM is guaranteed by the error correction information, but data that is not accessed is not guaranteed against errors. Accordingly, because an address translation table stored in SRAM is not accessed during low power consumption mode involving halt of operation in a flash memory controller, the data cannot be verified by detecting and correcting any soft error that occurs during low power consumption mode. Moreover, during low power consumption mode involving reduced operating frequency too, a soft error cannot be detected unless data in an address translation table is accessed.
A soft error that has occurred during low power consumption mode can be first detected when error data in an address translation table is accessed after returning to regular mode. Therefore, if low power consumption mode continues for a long period of time, soft errors may accumulate in the address translation table and those errors may not be able to be corrected any more from the error correction information. In that case, it is necessary to access a flash memory chip connected to the flash memory controller, read address information, and reconfigure the address translation table in the SRAM. It takes about 1-2 seconds per flash memory chip to reconfigure the address translation table. Therefore, if a large number of chips are connected to a flash memory controller, it takes a long period of time to reconfigure the address translation table. For storage apparatuses, from which high speed access is required, a long time taken to reconfigure the address translation table when returning from low power consumption mode to regular mode is not acceptable.
Japanese Patent Laid-Open Publication No. 2003-337757 lacks consideration for lowering power consumption. Moreover, the technique disclosed in that document cannot address common soft errors that may occur in an address translation table. In other words, that technique is designed to prevent inappropriate mapping that may be made when a valid logical page address is garbled into a invalid logical page address. However, if a valid logical page address is garbled, generally speaking, it is not always garbled into a invalid logical page address. For example, it is possible that a valid logical page address is garbled into another valid logical page address. In that case, errors in the address translation table cannot be verified with the technique disclosed in Japanese Patent Laid-Open Publication No. 2003-337757.
The invention has been made in light of the above described points, and its object is to propose a flash memory module able to immediately return from low power consumption mode to regular mode by verifying data in an address translation table in the flash memory module during low power consumption mode, a storage apparatus using that flash memory module as a storage medium, and a method for verifying an address translation table in the flash memory module.